An embodiment of the present invention relates to a method for manufacturing a semiconductor device, and more specifically, to a method for manufacturing a semiconductor device including a vertical transistor.
Due to increase in integration of a semiconductor device, a channel length of a transistor has been gradually decreased. However, is the decrease in the channel length of the transistor causes short channel effects such as a drain induced barrier lowering (DIBL) phenomenon, a hot carrier effect and a punch through phenomenon. In order to prevent the short channel effects, various methods have been suggested, i.e. a method of reducing a depth of a junction region or a method of forming a recess in a channel region of a transistor to increase a channel length.
However, as integration density of a semiconductor memory device, specifically, DRAM is edged up to giga bit, a smaller-sized transistor is required. That is, a transistor of DRAM having giga bit requires a unit cell area of less than 8F2 (F: minimum feature size) or of 4F2. As a result, it is difficult to satisfy the required unit cell area even though a channel length of a current plannar-structured transistor is scaled down that comprises a gate electrode formed over a semiconductor substrate and a junction region formed at both sides of the gate electrode. In order to meet the unit cell size requirement, a vertical channel transistor structure has been suggested.
In the vertical channel transistor, a source/drain region is formed in upper and lower portions of a silicon pillar, and a body (where a channel is formed) of the transistor is electrically floated. This configuration causes off-state leakage. That is, even when the transistor is not activated, holes which are positive charges are piled up in the body due to gate induced drain leakage (GIDL) or hot carrier injection. As a result, a threshold voltage of the transistor is lowered, and off-leakage of the transistor is increased. These phenomena cause mal-operation of a logic circuit and loss of information from a cell capacitor.